1. Field of the Invention
This invention relates to semiconductor devices and more particularly to a method of fabricating a six transistor SRAM cell and the resulting SRAM cell structure.
2. Description of the Prior Art
As is well known in the art, all metal oxide semiconductor (MOS) static random access memories (SRAMs) have in common a basic cell consisting of two transistors and two load elements in a flip-flop configuration, together with two select transistors.
FIG. 1 is a schematic circuit diagram of a six transistor (6-T) SRAM cell 1 in the prior art. SRAM cell 1 includes N type MOS (NMOS) transistors N1 and N2 (hereinafter transistors N1 and N2) coupled between V.sub.SS (typically ground) and nodes A and B, respectively. Nodes A and B are further coupled to V.sub.DD (typically 5.0 volts (V) or 3.3 V) by pullup P type MOS (PMOS) transistors P1 and P2 (hereinafter transistors P1 and P2), respectively. Node A is further coupled to the gates of transistors P2 and N2 and node B is similarly coupled to the gates of transistors P1 and N1.
Information is stored in SRAM cell 1 in the form of voltage levels in the flip-flop formed by the two cross-coupled inverters 2 and 3 formed by transistors P1, N1 and P2, N2, respectively. In particular, when node A is at a logic low state (the voltage of node A being approximately equal to V.sub.SS), transistor P2 is on (in a low resistance state or conducting) and transistor N2 is off (in a high resistance state or non conducting). When transistor P2 is on and transistor N2 is off, node B is at a logic high state (the voltage of node B is pulled up to approximately V.sub.DD). Further, when node B is at a logic high state, transistor P1 is off and transistor N1 is on. When transistor P1 is off and transistor N1 is on, node A is at a logic low state (the voltage of node A is pulled down to approximately V.sub.SS). In this manner, SRAM cell 1 remains in a latched state.
Nodes A and B are further coupled to a Bit line and a Bit line by NMOS select transistors N3 and N4 (hereinafter transistors N3 and N4), respectively. The gates of transistors N3 and N4 are coupled to a word line to enable read and write operations as those skilled in the art will understand.
One important characteristic of an SRAM cell is its size (surface area on an integrated circuit chip). Generally, it is desirable to reduce the size of the SRAM cell thereby allowing a higher density SRAM to be fabricated. Referring to FIG. 1, to fabricate a conventional 6-T SRAM cell, NMOS transistors N1, N2, N3, N4 and PMOS transistors P1, P2 are fabricated in a semiconductor substrate, typically silicon.
FIG. 2 is a cross-sectional view of a conventional lightly doped drain (LDD) complimentary metal oxide semiconductor (CMOS) structure 4 used in conventional 6-T SRAM cells. As shown in FIG. 2, a P-well 5 and an N-well 6 are formed in a semiconductor substrate 7. Formed at the surface of substrate 7 are field oxide regions 8. Formed above P-well 5 and N-well 6 are gate oxide layers 9.
Formed over gate oxide layers 9 are conductive gates 10 of NMOS transistor 11 and PMOS transistor 12. As shown in FIG. 2, LDD N type source/drain regions 13 of NMOS transistor 11 consist of N- lightly doped source/drain regions 14 laterally aligned (self aligned) to gate 10 and N+ heavily doped source/drain regions 15 laterally aligned (self aligned) to sidewall spacers 16. Similarly, LDD P type source/drain regions 17 of PMOS transistor 12 consist of P- lightly doped source/drain regions 18 laterally aligned (self aligned) to gate 10 and P+ heavily doped source/drain regions 19 laterally aligned (self aligned) to sidewall spacers 16.
CMOS structure 4 requires the formation of N type and P type active regions (field oxide regions 8 define the active regions, i.e. the active regions are in between field oxide regions 8) in the semiconductor substrate and also requires formation of field oxide regions 8 between the active regions to electrically isolate the active regions from one another. Each of the regions require a certain amount of chip area.
One method of reducing the size of an SRAM cell is to substitute a four transistor, two resistor SRAM cell (4-T, 2-R SRAM cell). As is well known to those skilled in the art, in a 4-T, 2-R SRAM cell, transistors P1 and P2 (FIG. 1) are replaced with resistor loads (not shown). However, as higher DC current is drawn through the resistor load (as compared to the PMOS transistor P1 or P2) of the invertor 2 or 3 having its NMOS transistor N1 or N2 on, respectively, 4-T, 2-R SRAM cells consume a large amount of standby power compared to 6-T SRAM cells. Yet, it is desirable to minimize the standby power consumed by an SRAM cell.
Another method to reduce the size of an SRAM cell is to fabricate a thin-film transistor (TFT) SRAM cell in which the PMOS transistors (P1 and P2 of FIG. 1) are stacked in a polysilicon interconnect layer, as is well known to those skilled in the art. Although TFT SRAM cells consume less standby power than 4-T, 2-R SRAM cells, TFT SRAM cells still consume more standby power than 6-T SRAM cells. Further, fabrication of a TFT SRAM cell requires additional processing steps compared to a 6-T SRAM cell thereby adding to the complexity and cost of fabricating the SRAM.
Accordingly, there is needed a relatively simple method of fabricating low power 6-T SRAM cells which occupy less chip area.